A DMOS (Double Diffused MOS) transistor is a type of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that uses diffusion to form the transistor region. DMOS transistors are typically employed as power transistors for power integrated circuits. DMOS transistors provide high current per unit area where low forward voltage drops are required.
One particular type of DMOS transistor is a so-called “trench” DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon (i.e., polycrystalline silicon), allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931, which are incorporated herein by reference.
The trench DMOS transistor may include a plurality of interconnected trenches form on a semiconductor substrate. At least one of the interconnected trenches constitutes a shielded gate trench (SGT) structure, which includes a trenched gate disposed on an upper portion of the SGT structure and a bottom shielding electrode disposed on a bottom portion of the SGT structure insulated from the trenched gate.
FIG. 1 is a cross-sectional view illustrating a prior art SGT DMOS 100. The SGT DMOS 100 includes an N+ substrate 101 functioning as a drain electrode, a drain layer 102, upon which is grown a lightly doped N− epitaxial layer 104 of a predetermined depth. Within the N-epi layer 104, P− body region 106 (p, p+) is provided. In the design shown, the P− body region 106 is substantially planar, lying below the top surface of the N− epitaxial layer 104. Another layer 108 (n+) overlying most of the p-body region 106 serves as source. A trench 109 is provided in the N− epitaxial layer 104, opening toward the top and having a predetermined depth. The trench 109 is typically lined with oxide and filled with conductive polysilicon, forming a trenched gate 110 and a gate shield 112 for the DMOS device 100. Examples of trench SGT DMOS transistors are disclosed in U.S. Pat. Nos. 5,283,201, 5,578.508, 5,998,833 and 6,388,286, which are incorporated herein by reference.
A problem with prior art trench DMOS transistors is that the channel mobility tends to remain low (especially P channel devices) due to the limited mobility of silicon. Especially for low voltage applications, this results in relatively high drain-source resistance (Rdson) since the channel resistance dominates operation of the DMOS transistors in such applications. There is no improvement in mobility for standard MOSFETs, therefore, drain to source resistance Rdson can be significant at low voltages.
Planar devices are typically used in integrated circuits. Unfortunately, in addition to relatively low channel mobility, planar MOSFETs tend to have a large cell pitch because of the horizontal structure of the channel and drain, source and gate. Improvements in Planar MOSFETs have been reported which incorporate means of increasing the channel mobility. Certain improvements may involve the use of a Silicon-Germanium (SiGe) channel or a strained channel. These devices are still planar in nature however and tend to have a large cell pitch, and relatively high “Rdson*Area” figure of merit
It is within this context that embodiments of the present invention arise.